/*
 * Copyright (c) 2025 Core Devices LLC
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef INCLUDE_ZEPHYR_DT_BINDINGS_DMA_SF32LB52X_DMA_H_
#define INCLUDE_ZEPHYR_DT_BINDINGS_DMA_SF32LB52X_DMA_H_

#include "sf32lb-dma-config.h"

#define SF32LB52X_DMA_REQ_MPI1              0U
#define SF32LB52X_DMA_REQ_MPI2              1U
#define SF32LB52X_DMA_REQ_I2C4              3U
#define SF32LB52X_DMA_REQ_USART1_TX         4U
#define SF32LB52X_DMA_REQ_USART1_RX         5U
#define SF32LB52X_DMA_REQ_USART2_TX         6U
#define SF32LB52X_DMA_REQ_USART2_RX         7U
#define SF32LB52X_DMA_REQ_GPTIM1_UPDATE     8U
#define SF32LB52X_DMA_REQ_GPTIM1_TRIGGER    9U
#define SF32LB52X_DMA_REQ_GPTIM1_CC1        10U
#define SF32LB52X_DMA_REQ_GPTIM1_CC2        11U
#define SF32LB52X_DMA_REQ_GPTIM1_CC3        12U
#define SF32LB52X_DMA_REQ_GPTIM1_CC4        13U
#define SF32LB52X_DMA_REQ_BTIM1             14U
#define SF32LB52X_DMA_REQ_BTIM2             15U
#define SF32LB52X_DMA_REQ_ATIM1_UPDATE      16U
#define SF32LB52X_DMA_REQ_ATIM1_TRIGGER     17U
#define SF32LB52X_DMA_REQ_ATIM1_CC1         18U
#define SF32LB52X_DMA_REQ_ATIM1_CC2         19U
#define SF32LB52X_DMA_REQ_ATIM1_CC3         20U
#define SF32LB52X_DMA_REQ_ATIM1_CC4         21U
#define SF32LB52X_DMA_REQ_I2C1              22U
#define SF32LB52X_DMA_REQ_I2C2              23U
#define SF32LB52X_DMA_REQ_I2C3              24U
#define SF32LB52X_DMA_REQ_ATIM1_COM         25U
#define SF32LB52X_DMA_REQ_USART3_TX         26U
#define SF32LB52X_DMA_REQ_USART3_RX         27U
#define SF32LB52X_DMA_REQ_SPI1_TX           28U
#define SF32LB52X_DMA_REQ_SPI1_RX           29U
#define SF32LB52X_DMA_REQ_SPI2_TX           30U
#define SF32LB52X_DMA_REQ_SPI2_RX           31U
#define SF32LB52X_DMA_REQ_I2S1_TX           32U
#define SF32LB52X_DMA_REQ_I2S1_RX           33U
#define SF32LB52X_DMA_REQ_PDM1_L            36U
#define SF32LB52X_DMA_REQ_PDM1_R            37U
#define SF32LB52X_DMA_REQ_GPADC             38U
#define SF32LB52X_DMA_REQ_AUDADC_CH0        39U
#define SF32LB52X_DMA_REQ_AUDADC_CH1        40U
#define SF32LB52X_DMA_REQ_AUDAC_CH0         41U
#define SF32LB52X_DMA_REQ_AUDAC_CH1         42U
#define SF32LB52X_DMA_REQ_GPTIM2_UPDATE     43U
#define SF32LB52X_DMA_REQ_GPTIM2_TRIGGER    44U
#define SF32LB52X_DMA_REQ_GPTIM2_CC1        45U
#define SF32LB52X_DMA_REQ_AUDPRC_TX_OUT_CH1 46U
#define SF32LB52X_DMA_REQ_AUDPRC_TX_OUT_CH0 47U
#define SF32LB52X_DMA_REQ_AUDPRC_TX_CH3     48U
#define SF32LB52X_DMA_REQ_AUDPRC_TX_CH2     49U
#define SF32LB52X_DMA_REQ_AUDPRC_TX_CH1     50U
#define SF32LB52X_DMA_REQ_AUDPRC_TX_CH0     51U
#define SF32LB52X_DMA_REQ_AUDPRC_RX_CH1     52U
#define SF32LB52X_DMA_REQ_AUDPRC_RX_CH0     53U
#define SF32LB52X_DMA_REQ_GPTIM2_CC2        54U
#define SF32LB52X_DMA_REQ_GPTIM2_CC3        55U
#define SF32LB52X_DMA_REQ_GPTIM2_CC4        56U
#define SF32LB52X_DMA_REQ_SDMMC1            57U

#endif /* INCLUDE_ZEPHYR_DT_BINDINGS_DMA_SF32LB52X_DMA_H_ */
